The present invention relates to a method for fabricating a semiconductor device, more specifically a method for fabricating a semiconductor device having a transistor and a resistance element.
In semiconductor devices, one of elements used in analog circuits, etc. is a resistance element of polysilicon. Usually the resistance element of polysilicon is formed of polysilicion film used for forming the gate electrodes, concurrently with forming the gate electrodes. Generally, the resistance value of the resistance element of polysilicon is adjusted as required, by ion implantation of a dopant.
On the other hand, in logic devices, generally the gate electrodes and the source/drain regions of the transistors are silicided. Here, in forming the resistance elements concurrently with forming the transistors, silicide block for covering the resistance elements with silicon oxide film is performed for the prevention of siliciding the resistance elements before the step of siliciding the gate electrodes, etc.
In the silicide block the resistance elements are covered with silicon oxide film. Accordingly, it is necessary to implant ions for adjusting a resistance value of the resistance elements prior to the silicide block.
Conventionally, the ion implantation for adjusting resistance values of such resistance elements have been performed before the gate electrodes and the resistance elements are processed (see, e.g., Japanese Patent Application Laid-Open Publication No. 2001-7220, Japanese Patent Application Laid-Open Publication No. Hei8-148649 (1996), Japanese Patent Application Laid-Open Publication No. Hei10-150154 (1998) and Japanese Patent Application Laid-Open Publication No. 2001-168281).
First, a polysilicon film which is to form the gate electrodes and the resistance elements is formed on a semiconductor substrate.
Then, dopant ions are implanted into regions of the polysilicon film for the gate electrodes to be formed in and into regions of the polysilicon film for the resistance elements to be formed in.
Then, the polysilicon film is etched to form the gate electrodes and the resistance elements.
Then, the source/drains, etc. of the transistors are formed by the usual semiconductor fabrication process, and the resistance elements are formed concurrently with forming the transistors.
As described above, conventionally, in forming the resistance elements concurrently with forming the transistors, the regions of the polysilicon film for the transistors to be formed in and the regions of the polysilicon film for the resistance elements to be formed in are doped before the gate electrodes are formed.
However, in forming CMOS transistors, n type doping and p type doping make the etching mechanism of the polysilicon film different between the n type doped regions and the p type doped regions. This has made it difficult to process the n type gate electrodes and the p type gate electrodes into the same configuration.